Hardware Implementation of an Iterative Parallel Scheduler for Optical Interconnection Networks

TY - JOUR

T1 - Hardware Implementation of an Iterative Parallel Scheduler for Optical Interconnection Networks

AU - Corvera, Jan Alain

AU - Dumlao, Samuel Matthew G

AU - Reyes, Rosula SJ

AU - Castoldi, Piero

AU - Andriolli, Nicola

AU - Cerutti, Isabella

N1 - J. A. Corvera, S. M. G. Dumlao, R. Reyes, P. Castoldi, N. Andriolli, and I. Cerutti, "Hardware Implementation of an Iterative Parallel Scheduler for Optical Interconnection Networks," in Advanced Photonics 2016 (IPR, NOMA, Sensors, Networks, SPPCom, SOF), OSA Technical Digest (online) (Optical Society of America, 2016), paper NeM3B.4.

PY - 2016/1/1

Y1 - 2016/1/1

KW - Algorithms

KW - Field programmable gate arrays

KW - Optical networks

UR - https://archium.ateneo.edu/ecce-faculty-pubs/56

UR - https://www.osapublishing.org/abstract.cfm?uri=Networks-2016-NeM3B.4

M3 - Article

JO - Electronics, Computer, and Communications Engineering Faculty Publications

JF - Electronics, Computer, and Communications Engineering Faculty Publications

ER -