FPGA Implementation of a Telecommunications Trainer System

TY - JOUR

T1 - FPGA Implementation of a Telecommunications Trainer System

AU - Oppus, Carlos

AU - Monje, Jose Claro N

AU - Reyes, Rosula SJ

AU - Patron, Noel S

AU - Guerrero, Reynaldo C

AU - Fajardo, Jovilyn Therese B

N1 - Reyes, R., Oppus, C., Monje, J., Patron, N., Guerrero, R., & Fajardo, J. (2008). FPGA Implementation of a Telecommunications Trainer System. International Journal of Circuits, Systems and Signal Processing, 2(1), 87-94.

PY - 2008/1/1

Y1 - 2008/1/1

KW - field programmable gate array

KW - telecommunications trainer

KW - digital modulation

KW - analog modulation

KW - encoding techniques

KW - keying

UR - https://archium.ateneo.edu/discs-faculty-pubs/196

M3 - Article

JO - Department of Information Systems & Computer Science Faculty Publications

JF - Department of Information Systems & Computer Science Faculty Publications

ER -