FPGA Implementation of a Telecommunications Trainer System

Carlos Oppus; Jose Claro N Monje; Rosula SJ Reyes; Noel S Patron; Reynaldo C Guerrero; Jovilyn Therese B Fajardo

FPGA Implementation of a Telecommunications Trainer System

Carlos Oppus, Jose Claro N Monje, Rosula SJ Reyes, Noel S Patron, Reynaldo C Guerrero, Jovilyn Therese B Fajardo

Ateneo de Manila University

Research output: Contribution to journal › Article › peer-review

Original language	American English
Journal	Department of Information Systems & Computer Science Faculty Publications
State	Published - Jan 1 2008

Keywords

field programmable gate array
telecommunications trainer
digital modulation
analog modulation
encoding techniques
keying

Disciplines

Computer Sciences

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FPGA Implementation of a Telecommunications Trainer SystemFinal published version, 607 KBLicense: Unspecified
FPGA Implementation of a Telecommunications Trainer SystemFinal published version, 607 KBLicense: Unspecified

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@article{95fea117e93c415f978fe132e5d5f574,

title = "FPGA Implementation of a Telecommunications Trainer System",

keywords = "field programmable gate array, telecommunications trainer, digital modulation, analog modulation, encoding techniques, keying",

author = "Carlos Oppus and Monje, {Jose Claro N} and Reyes, {Rosula SJ} and Patron, {Noel S} and Guerrero, {Reynaldo C} and Fajardo, {Jovilyn Therese B}",

note = "Reyes, R., Oppus, C., Monje, J., Patron, N., Guerrero, R., & Fajardo, J. (2008). FPGA Implementation of a Telecommunications Trainer System. International Journal of Circuits, Systems and Signal Processing, 2(1), 87-94.",

year = "2008",

month = jan,

day = "1",

language = "American English",

journal = "Department of Information Systems & Computer Science Faculty Publications",

}

TY - JOUR

T1 - FPGA Implementation of a Telecommunications Trainer System

AU - Oppus, Carlos

AU - Monje, Jose Claro N

AU - Reyes, Rosula SJ

AU - Patron, Noel S

AU - Guerrero, Reynaldo C

AU - Fajardo, Jovilyn Therese B

N1 - Reyes, R., Oppus, C., Monje, J., Patron, N., Guerrero, R., & Fajardo, J. (2008). FPGA Implementation of a Telecommunications Trainer System. International Journal of Circuits, Systems and Signal Processing, 2(1), 87-94.

PY - 2008/1/1

Y1 - 2008/1/1

KW - field programmable gate array

KW - telecommunications trainer

KW - digital modulation

KW - analog modulation

KW - encoding techniques

KW - keying

UR - https://archium.ateneo.edu/discs-faculty-pubs/196

M3 - Article

JO - Department of Information Systems & Computer Science Faculty Publications

JF - Department of Information Systems & Computer Science Faculty Publications

ER -

FPGA Implementation of a Telecommunications Trainer System

Keywords

Disciplines

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